ABB UFC718AE01 HIEE300936R0101

是一种频繁地填充指令流水线的控制模块，它采用了超标量CPU体系结构设计。这种体系结构设计的最大困难在于创建一个有效的调度程序，它需要能够快速确定指令是否可以并行执行，并以尽可能多的执行单元保持忙碌的方式来调度它们。这要求尽可能频繁地填充指令流水线，并且需要大量的CPU缓存。此外，为了保持高水平的性能，还需要采用危险-避免、投机执行、寄存器重命名、无序执行和事务内存等技术分支预测。

It is a control module that frequently fills the instruction pipeline and adopts a superscalar CPU architecture design. The biggest difficulty in designing this architecture lies in creating an effective scheduler that needs to be able to quickly determine whether instructions can be executed in parallel and schedule them in a busy manner with as many execution units as possible. This requires filling the instruction pipeline as frequently as possible and requires a large amount of CPU cache. In addition, in order to maintain a high level of performance, it is necessary to use techniques such as danger avoidance, speculative execution, register renaming, unordered execution, and transaction memory for branch prediction.